Xilinx rtl schematic not updating
This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.Hardware/software (HW/SW) cosimulation integrates software simulation and hardware simulation simultaneously.Usually, HW/SW co-simulation platform is used to ease debugging and verification for very large-scale integration (VLSI) design.
The major contributions of this work are: (1) a novel design of memory controller in the Verilog Hardware Description Language (Verilog HDL) to reduce memory consumption and load on the processor.
(2) The testing part of the neural network algorithm is being hardwired to improve the speed and performance.
The American Sign Language gesture recognition is chosen to verify the performance of the approach.
Several experiments were carried out on four databases of the gestures (alphabet signs A to Z).
(3) The major benefit of this design is that it takes only few milliseconds to recognize the hand gesture which makes it computationally more efficient.
In today’s world, the field programmable gate array (FPGA) technology has advanced enough to model complex chips replacing custom application-specific integrated circuits (ASICs) and processors for signal processing and control applications.FPGAs are preferred as higher-level tools evolve to deliver the benefits of reprogrammable silicon to engineers and scientists at all levels of expertise.Taking advantage from the current FPGA technology, this paper proposes a hardware/software cosimulation methodology using hardware description language (HDL) simulations on FPGA as an effort to accelerate the simulation time and performance [1, 2].The conventional software simulation method has more flexibility in terms of parameters variation.The desired simulation parameters can be changed to study the system behavior under various conditions.The major drawback with the conventional approach is the intolerable simulation time.